1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a plurality of pairs of data lines to each of which a plurality of pairs of digit lines are connected and a clamp circuit for clamping or setting the voltages of the data lines at a predetermined levels.
2. Description of Related Art
FIG. 1 shows a circuit diagram of a data read section in a conventional semiconductor memory device. In FIG. 3, a memory cell 4 comprises NMOS transistors 5 to 8 and resistors 9 and 10. The NMOS transistor 7 has a source connected to a low power-source voltage VS2, and a drain and a gate connected to a gate and a drain of the NMOS transistor 8, respectively. The NMOS transistor 8 has a source connected to the low power-source voltage VS2 and a drain and a gate connected to the gate and the drain of the NMOS transistor 7, respectively. The resistor 9 is connected between a second high power-source voltage Vcc2 and the drain of the NMOS transistor 7. The resistor 10 is connected between the second high power-source voltage Vcc2 and the drain of the NMOS transistor 8. The NMOS transistor 5 has a gate connected to a word line 109 and a source and a drain connected to a digit line 101 and the drain of the NMOS transistor 7. The NMOS transistor 6 has a gate connected to a word line 109 and a source and a drain connected to the digit line 102 and the drain of the NMOS transistor 8.
A digit line block la comprises a pair of digit lines 101 and 102, PMOS transistors 2, 3, 11, and 12, and a plurality of memory cells 4. The PMOS transistor 2 has a gate connected to a second low power-source voltage VS2 and a source connected to the second high power-source voltage Vcc2, and a drain connected to the digit line 101. The PMOS transistor 3 has a gate connected to the second low power-source voltage VS2, a source connected to the second high power-source voltage Vcc2, and a drain connected to the digit line 102. The PMOS transistor 11 has a gate connected to the digit selecting line 111 and a source and a drain connected to the digit line 101, and a first data line 103, respectively. The PMOS transistor 12 has a gate connected to the digit selecting line 111, and a source and a drain connected to a digit line 102 and a first data line 105. The memory cells 4 are connected to a word line 109 and the digit lines 101 and 102. The digit selecting lines 111 to 114 are used for selecting one of the digit line blocks 1a to 1d.
In a conventional memory semiconductor device, a plurality of word lines are provided and a plurality of memory cells are connected to a pair of digit lines. FIG. 1 shows, however, only a single memory cell connected to a single word line and a pair of digit lines for easy understanding.
Each of the digit line blocks 1b to 1d has the same arrangement as that of the digit line block 1a except the followings:
The gates of the PMOS transistors 11 and 12 of the digit line block 1b are connected to a digit selecting line 112. The gates of the PMOS transistors 11 and 12 of the digit line block 1c are connected to a digit selecting line 113, and the drains of the PMOS transistors 11 and 12 are connected to the first data lines 104 and 106, respectively. The gate of the PMOS transistor 11 of the digit line block 1d is connected to a digit selecting line 114, and the drains of the PMOS transistors 11 and 12 are connected to the first data lines 104 and 106, respectively.
The first data lines 103 and 105 transmit data read out from the memory cells within the digit line blocks 1a and 1b to second data lines 107 and 108, respectively. The first data lines 104 and 106 transmit data read out from the memory cells within the digit line blocks 1c and 1d to the second data lines 107 and 108, respectively.
The first data lines 103 and 105 are connected to the bases of the NPN transistors 13 and 14, respectively. A collector of the NPN transistor 13 is connected to a first high power-source voltage Vcc1 and an emitter of which is connected to the second data line 107. A collector of the NPN transistor 14 is connected to the first high power-source voltage Vcc1 and an emitter of which is connected to the second data line 108.
Similarly, the first data lines 104 and 106 are connected to the bases of the NPN transistors 15 and 16, respectively. A collector of the NPN transistor 15 is connected to the first high power-source voltage Vcc1 and an emitter of which is connected to the second data line 107. A collector of the NPN transistor 16 is connected to the first high power-source voltage Vcc1 and an emitter of which is connected to the second data line 108. The second data lines 107 and 108 transmit data transmitted from the first data lines 103 or 105, and 104 or 106 to a sense amplifier SA.
The PMOS transistors 35 to 38 clamp or set the non-selected first data lines at a predetermined voltage in accordance with voltage values of block selecting lines 115 and 116. The gate of the PMOS transistor 35 is connected to the block selecting line 115. One of the remaining two terminals of the PMOS transistor 35 is connected to a clamp control line 110 and the other is connected to the first data line 103. The gate of the PMOS transistor 36 is connected to the block selecting line 115 and one of the remaining two terminals is connected to the clamp control line 110 and the other is connected to the first data line 105.
The gate of the PMOS transistors 37 is connected to the block selecting line 116. One of the remaining two terminals of the PMOS transistor 37 is connected to the clamp control line 110 and the other is connected to the first data line 104. A gate of the PMOS transistor 38 is connected to the block selecting line 116. One of the remaining two terminals of the PMOS transistor 38 is connected to the clamp control line 110 and the other is connected to the first data line 106.
The second data lines 107 and 108 are connected to the bases of NPN transistors 21 and 22 serving as input transistors of the sense amplifier SA. The collectors of the NPN transistors 21 and 22 are connected to the first high power-source voltage Vcc1. Further, the emitters of the NPN transistors 21 and 22 are connected to the drains of the NMOS transistors 27 and 29, respectively. The emitters of the NPN transistors 23 and 24 are connected to the drain of the NMOS transistor 28. The collector of the NPN transistor 23 is connected to the first high power-source voltage Vcc1 through a resistor 25 and a base of which is connected to the emitter of the NPN transistor 21. The collector of the NPN transistor 24 is connected to the first high power-source voltage Vcc1 through a resistor 26 and a base of which is connected to the emitter of the NPN transistor 22. A node of the resistor 25 and the collector of the NPN transistor 23 and a node of the resistor 26 and the collector of the NPN transistor 24 serve as sense outputs 201 and 202, respectively. The gates of the NMOS transistors 27 to 29 are connected to a reference voltage Vr and sources of which are connected to a first low power-source voltage Vs1.
A read operation of the memory circuit shown in FIG. 1 will now be described. Assume now that the memory cell 4 in the digit line block la is in a selected state and the NMOS transistor 7 is in an ON state.
A decoder (a column decoder) not shown sets one of the digit selecting lines 111 to 114 to a low level and the remaining three lines to a high level in response to an externally supplied column address signal.
Similarly, a decoder (a row decoder) not shown selects one of plurality of word lines, sets the selected word line and non-selected word lines to high and low levels, respectively in response to an externally supplied row address signal. Assume now that the word line 109 is in the selected state and in the high level state.
In the memory cell 4 of the selected digit line block 1a, the NMOS transistor 7 is in the ON state; the NMOS transistor 8 is in the OFF state; and the memory cell 4 is in a stable state.
The voltages of the digit lines 101 and 102 are determined by the currents flowing into the first data lines 103 and 105, and the current flowing into the memory cell 4.
The voltages of the first data lines 103 and 105 are transmitted to the second data lines 107 and 108 through the NPN transistors 13 and 14 and applied to a sense amplifier SA using a differential operational amplifier.
If the PMOS transistors 35 to 38 are assumed not to be provided, the first data lines 104 and 105 in the non-selected state (to which the selected digit block selecting line 1a is not connected) goes to a floating state electrically and the voltages thereof becomes unstable.
If the voltages of the first data lines 104 and 106 become an abnormally low voltage due to some cause and the selected digit line block is switched from the digit line block 1a to the digit line block 1c or 1d, a time period for reading data from the memory cell will become longer or data might be erroneously written in the memory cell.
More specifically, when the voltages of the first data lines 104 and 106 become a voltage lower than the voltage of the data line 103 to which the selected digit line block 1a is connected by an intermediate voltage between the second high power-source voltage Vcc2 and the low power-source voltage Vs2 (or a voltage lower than the intermediate voltage), and when the selected digit line block 1a is switched to the digit line block 1c or 1d, the read time might be longer since it takes too much time to charge the first data lines 104 and 106 or the voltages of the first data lines 104 and 106 may change the voltages of the newly selected digit lines 101 and 102 so that the data might be erroneously written in the memory cell. The voltage of the data line 103 is a lower-side one of the voltages of the first data lines 103 and 105 to which the selected digit line block 1a is connected. The voltage of the data line 103 is lower than the second high power source Vcc2 by O.1 V to 0.2 V.
In order to prevent such problem, in the semiconductor memory device shown in FIG. 1, clamping transistors 35 to 38 are provided. The voltage of the clamp control line 110 is set at a voltage equal to or slightly lower than a voltage of the line at the low voltage side of the first data lines 103 and 105 to which the selected digit line block 1a is connected; the block selecting line 115 is set at a high level and the PMOS transistors 35 and 36 are cut off to electrically isolate the first data lines 103 and 105, and the clamp control line 110. Further, the block selecting line 116 is set at a high level and the PMOS transistors 37 and 38 are turned on to clamp the voltages of the first data lines 104 and 106 at the one approximately equal to the voltage of the clamp control line 110. Such arrangement permits the voltages of the first data lines 104 and 106 in the non-selected state to be fixed without affecting the voltages of the first data lines 103 and 105 in the selected state.
However, in the semiconductor memory device having the above arrangement, the block selecting lines 115 and 116, a circuit for identifying the selected and non-selected states of the data line pairs, a circuit for controlling the voltages of the block selecting lines and the like must be provided, resulting in increased circuit size and complicated circuit structure.